1. Field of the Invention
The invention relates to the protection of integrated circuits from electrostatic discharge (ESD), and more particularly to structures for the to protection from ESD by adding P-ESD implants and an additional N-well to the drains of an off-chip driver (OCD) NMOS transistor.
2. Description of the Related Art
The protection of integrated circuits from electrostatic discharge (ESD) has received a lot of attention. Many researchers in this field have proposed solutions to protect submicron devices without requiring any increase of silicon real estate. FIG. 1a depicts a cross-section of the related art showing in a P+ substrate 12 an OCD NMOS transistor A with N+ source 14a, drain 16a, a gate 18a, and a P+ type diffusion 20a. The source 14a, the gate 18a, and P+ substrate 12 (via P+ type diffusion 20a) are shown tied to ground (GND). An ESD pulse VTLP at point P is shown discharging into drain 16a with current ITLP. An N-ESD implant 17, typically a blanket implant covering the entire active area (source 14a and drain 16a) of the transistor, is applied to make the junction more graded. Such a technique is known to improve the ESD performance of NMOS transistors by reducing the current density in graded junctions and thus improving the value of It2 (second breakdown current). Unfortunately, such a solution does nothing to decrease the avalanche voltage (Vt1) of the transistor, thus making multifinger turn-on very difficult, as illustrated in FIG. 1b where the current ITLP is graphed against the voltage VTLP. In this and subsequent graphs, subscript ‘t1’ indicates the avalanche point indicated by Point A, subscript ‘sp’ indicates the point of snapback indicated by Point SP, and subscript ‘t2’ indicates the second breakdown voltage point indicated by Point B.
Another approach used is depicted in FIG. 2a. Here the gate G of MOSFET transistor N is coupled to the drain D through the RC network (of capacitor C and resistor R) such that part of the ESD voltage is coupled to the gate G to turn on the channel of the MOSFET transistor N. An ESD pulse VTLP at Point P is shown discharging into drain D. This approach, although efficient in reducing the Vt1 of the transistor N, requires additional chip area for the resistor R because it is typically very large. Furthermore, It2 is known to decrease with gate voltage, so the amount of coupling required needs to be accurately known to get good ESD performance of such an arrangement. FIG. 2b depicts the graph of such an arrangement, where the current ITLP is graphed against the voltage VTLP. Points A and B depicts the same points as those of FIG. 1b. 
FIG. 3 shows the same NMOS OCD A as FIG. 1a but with a second NMOS OCD B comprising source 14b, drain 16b, and gate 18b. The second NMOS OCD B is arranged in a mirror image to the first NMOS OCD A and with a second P+ type diffusion 32 floating in the middle of the N+ sources 14a, 14b. The intent of such a P+ diffusion is to increase the resistance the discharge current must travel to reach the ground potential (GND). This has the benefit of lowering the snapback voltage (Vsp) but has no effect in lowering Vt1 (avalanche voltage). However, lowering the snapback voltage does help in lowering It2 as the power product at breakdown is generally lower. Also shown are parasitic transistors Q1, Q2, and P+ substrate bulk resistors Rsub2 and Rsub2.
The inventions of the related art cited here do not decrease the avalanche breakdown voltage of the ESD devices without the use of additional circuit elements such as resistors. As a result, Vt2 (second breakdown voltage) of the ESD device is oftentimes lower than Vt1, resulting in the issue of multifinger turn-on. Furthermore, it is known that Vt1 is generally higher than the gate oxide breakdown voltage for submicron MOSFETSs and if nothing is done to reduce it will cause gate oxide damage even during the brief time for the transistor to turn on. Additionally, even if the gate oxide is not damaged it will cause significant hot carrier degradation, resulting in poor drive of the OCD as time goes on. The proposed invention is therefore a very desirable improvement in the field of ESD protection.
U.S. Patents relating to the subject of the present invention are:    U.S. Pat. No. 6,521,946 (Mosher) describes a doped region under a drain for ESD protection.    U.S. Pat. No. 6,365,932 (Kouno et al.) discloses a p-type base region in an N-well partly overlapping a deep N+ region.    U.S. Pat. No. 5,543,650 (Au et al.) shows an n-well with P+ implants for ESD protection.